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Computer System Architecture - Central Processing Unit

Avatto > > UGC NET COMPUTER SCIENCE > > PRACTICE QUESTIONS > > Computer System Architecture > > Central Processing Unit

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.
Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

21. Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is

  • Option : A
  • Explanation : The given program stores results from memory location 2000 to 2009.
    It stores values like 110,109,108.....100.
    No change at location 2010 So at 2010 value is 100
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Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.
Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

22. Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?

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23. A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2’s complement numbers 01001101 and 11101001. After the execution of this addition operation the status of the carry, overflow and sign flags, respectively will be :

  • Option : B
  • Explanation : 100110110 (in 2's complement ignore carry bit so ignore 1 at msb)
    After carry bit is ignored the value at msb is 0 means number is positive so sign bit is 0.
    Overflow flag is set only if the X-OR between the carry-into the sign bit and carry -out of the sign bit is 1.
    Therefore,
    carry flag = 1,
    overflow flag = 0,
    sign bit = 0
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24. Consider the following code sequences having five instructions I1 to I5. Each of these instructions has the following format.
OP, Ri, Rj, Rk
where operation OP is performed on contents of registers Rj and Rk and the result the stored in register Ri.
I1 : ADD R1, R2, R3
I2: MUL R7, R1, R3
I3 : SUB R4, R1, R5
I4 : ADD R3, R2, R4
I5 : MUL R7, R8, R9
Consider the following three statements :
S1 : There is an anti-dependence between instructions I2 and I5.
S2 : There is an anti-dependence between instructions I2 and I4.
S3 : Within an instruction pipeline an anti- dependence always creates one or more stalls.
Which one of the above statements is/are correct?

  • Option : B
  • Explanation : An antidependency also known as write-after-read (WAR) dependency.
    S1 is False, I2 and I5 they both write R7. So, No WAR.
    S2 is true, There is an anti-dependence between instructions I2 and I4.
    I2 reads R3 and I4 writes it.
    S3 is false.depends on how many instruction between the antidependence instructions.
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25. If we use internal data forwarding to speed up the performance of A CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations
R1 ￫ M[100]
M [100] ￫ R2
M [100] ￫ R3
can be replaced by

  • Option : D
  • Explanation : To achieve speedup we can transfer directly like the code given below.
    R1 ￫ R2
    R1 ￫ R3
    R1 ￫ M[100]
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Central Processing Unit