Computer System Architecture MCQ - Central Processing Unit

11 A 5 stage pipelined CPU has the following sequence of stages
IF - Instruction fetch from instruction memory.
RD - Instruction decode and register read,
EX - Execute : ALU operation for data and address computation.
MA - Data memory access – for write access the register read at RD stage it used,
WB - Register write back.
Consider the following sequence of instructions :
I₁ : L RO, Loc 1; RO ⇐ M[Loc1]
I₂ : A RO, RO; RO ⇐ RO + RO
I₃ : A R2, RO, R2 ⇐R2 – RO
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I₁?

Clock Cycles
central-processing

Consider the following data path of a CPU
The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cylces are needed for memory read operation – the first one for loading address in the MAR and the next one for loading data from the memory but into the MDR.

12 The instruction “add R0, R1” has the register transfer interpretation R0 < = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is

13 The instruction “call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is
Rn ⇐ PC + 1;
PC ⇐ M[PC];
The minimum number of CPU clock cycles needed during the execution cycle of this instruction is

14 The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is executed.

Which of the following below is TRUE after the program is executed ?

Rs = 1
Rd = 1
Rd = 1001
M[1001] = 20

15 A CPU has five-stages pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each instruction takes only cycle to complete on average, then total execution time of the program is

In the 3rd stage of pipeline, there will be 2 stall cycles i.e. 2 delay slots.
Total number of instructions = 109
= (0.2 * (2 + 1) + 0.8 * 1) * 10^9
= 1.4 sec