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Computer System Architecture - Central Processing Unit

Avatto > > UGC NET COMPUTER SCIENCE > > PRACTICE QUESTIONS > > Computer System Architecture > > Central Processing Unit

26. The data path shown in the figure computes the number of 1s in the 32-bit input word corresponding to an unsigned even integer stored in the shift register. The unsigned counter, initially zero, is incremented if the most significant bit of the shift register is 1.
The counter width (k), the number of missing microinstructions (n), and the control word for microinstructions I1, I2, ..., In are, respectively,

  • Option : D
  • Explanation : If number is even then LSB bit should be 0.
    So total 31 1’s for an unsigned EVEN integer.
    And 31 left shifts are needed to determine number of 1’s.
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27. Consider the following sequence of micro operations.
MBR ⇽ PC
MAR ⇽ X
PC ⇽ Y
Memory ⇽ MBR
Which one of the following is a possible operation performed by this sequence

  • Option : D
  • Explanation : Given: A sequence of micro operations
    MBR ⇽ PC
    MAR ⇽ X
    PC ⇽ Y
    Memory ⇽ MBR
    To find: What these micro operation represents?
    Analysis: On conver ting these operations to normal english
    1. First micro operation stores the value of PC into memory Base register (MBR)
    2. Second micro operation stores value of X into Memory Address register (MAR)
    3. Third micro operation stores value of Y into PC
    4. Fourth micro operation stores value of MBR to memory.
    So before execution of these instructions PC holds the value of next instruction to be executed. We first stores the value of PC to MBR and then through MBR to memory i.e. we are saving the value of PC in memory and then load PC with a new value. This can be done only in two types of operations conditional branch and interrupt service. As we are not checking here for any conditions so it is interrupt service.
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28. A micro program control unit is required to generate a total of 25 control signals. Assume that during any microinstruction at most two control signals are active. Minimum number of bits required in the control word to generate the required control signal

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Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

29. Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

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30. Consider that the memory is word addressable with size 32 bits and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs during the ADD instruction, what will be the return address pushed on to the stack.

  • Option : B
  • Explanation : If memory is word addressable then 1st instruction require two words space (1000 – 1001) 2nd instruction requires only 1 word space ( 1002) and instruction 3rd requires only 1 word space (1003) hence 3rd is add instruction and interrupt occurs during that so after executing that instruction CPU handles the interrupt so return address is 1004
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Central Processing Unit