Computer System Architecture MCQ - Central Processing Unit

A pipelined processor uses a 4-stage instruction pipeline with the following stages : Instruction fetch (IF), Instruction decode (ID), Executive (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S – R* (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.

central-processing

16 The number of Read-After-Write (RAW) dependencies, Write-After-Read (WAR) dependencies, and Write-After-Write (WAW) dependencies in the sequence of instructions are, respectively

Read After Write:
1. ADD ⇾ MUL (because of R5)
2. MUL ⇾ SUB (because of R6)
3. SUB ⇾ DIV (because of R5)
4. DIV ⇾ STORE (because of R6)
Write After Read
1. MUL ⇾ SUB (because of R5)
2. DIV ⇾ STORE (because of R6)
Write After Write
1. ADD ⇾ SUB (because of R5)
2. MUL – DIV (because of R6)

central-processing

17 The IF, ID and WB stages take 1 clock cycle each. The EX stage takes 1 clock cycle each for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV operations. Operand forwarding from the Ex stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is

18 A processor takes 12 cycles to complete an instruction 1. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?

19 Consider a pipelines processor with the following four stages
IF : Instruction Fetch
ID : Instruction Decode and Operand Fetch
Ex : Executive
WB : Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instruction need 1 clock cycle and the MUL instruction need 3 clock cycles in the Ex stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

For each of the three instruction four stages will be there. Since ,it is a pipelined processor, so one instruction may be fetched while other is being decoded or executed or written back action performed in each clock cycle may be represented as

Only, two instructions cannot be executed simultaneously.

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.
Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

20 Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is

Ist memory reference R1 ⇽ M[3000] and then in the loop which runs for 10 times, because the content of memory location 3000 is 10 given in question and loop will run 10 times as
{
R2 ⇽ M[R3]
M[R3] ⇽ R2
}
So Two memory reference every iteration
10 * 2 = 20
Total = 20 + 1 = 21