Computer System Architecture MCQ - Central Processing Unit

31 Consider a three word machine instruction ADD A[R₀], @ B
The first operand (destination) “a [RO]” uses indexed addressing mode with RO as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is

In Indexed addressing mode, the base address is already in the instruction i.e A and to fetch the index data from R0 no memory access is required because it’s a register So to fetch the operand only 1 memory cycle i s required. Indirect Addressing mode requires 2 memory cycles only

32 Data forwarding techniques can be used to speed up the operations in presence of data dependencies. Consider the following replacements of LHS with RHS.
(i) R1 ￫ Loc, Loc ￫ R2 ￫ R1 ￫ R2, R1 ￫ Loc
(ii) R1 ￫ Loc, Loc ￫ R2 ￫ R1 ￫ R2
(iii)R1 ￫ Loc, R2 ￫ Loc ￫ R1 ￫ Loc
(iv) R1 ￫ Loc, R2 ￫ Loc ￫ R2 ￫ Loc
In which of the following options, will be result of executing the RHS be the same as executing the LHS irrespective of the instructions that follow?

Only (i) Is true, as both registers and location are updated.

33 Following table indicates the latencies of operations between the instruction producing the result and instruction using the result.
What is the number of cycles needed to executed the above code segment assuming each instruction takes one cycle to execute?

34 Consider evaluating the following expressions tree on a machine with load-store architecture in which memory can be accessed only through load and store instructions. The variables a, b, c, d and e are initially stored in memory. The binary operators used in this expression tree can be evaluated by the machine only when the operands are in registers. The instructions produce result only in a register. If no intermediate results can be stored in memory, what is the minimum number of registers needed to evaluate this expression?

R1 ⇽ c, R2 ⇽ d, R2 ⇽ R1 + R2, R1 ⇽ e, R2 ⇽ R1- R2
Now to calculate the rest of the expression we must load a and b into the registers but we need the content of R2 later. So we must use another Register.
R1 ⇽ a, R3 ⇽ b, R1 ⇽ R1 – R3, R1 ⇽ R1 + R2

35 The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
1. function locals and parameters
2. register saves and restores
3. instruction fetches

I is true as by using multiple register windows, we eliminate the need to access the variable values again and again from the memory. Rather, we store them in the registers.