Central Processing Unit Q.24

24Consider the following code sequences having five instructions I1 to I5. Each of these instructions has the following format.
OP, Ri, Rj, Rk
where operation OP is performed on contents of registers Rj and Rk and the result the stored in register Ri.
I1 : ADD R1, R2, R3
I2: MUL R7, R1, R3
I3 : SUB R4, R1, R5
I4 : ADD R3, R2, R4
I5 : MUL R7, R8, R9
Consider the following three statements :
S1 : There is an anti-dependence between instructions I2 and I5.
S2 : There is an anti-dependence between instructions I2 and I4.
S3 : Within an instruction pipeline an anti- dependence always creates one or more stalls.
Which one of the above statements is/are correct?

Option : B
Explanation : An antidependency also known as write-after-read (WAR) dependency.
S1 is False, I2 and I5 they both write R7. So, No WAR.
S2 is true, There is an anti-dependence between instructions I2 and I4.
I2 reads R3 and I4 writes it.
S3 is false.depends on how many instruction between the antidependence instructions.

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