Computer System Architecture MCQ - Central Processing Unit

1 For a pipelined CPU with a single ALU, consider the following situations
1. The j + 1st instruction uses the result of the jth instruction as an operand
2. The execution of a conditional jump instruction
3. The jth and j + 1st instructions require the ALU at the same time
Which of the above can cause a hazard ?

(i) j + 1^st instruction uses result of the j^th instruction as an operand, then read-after- write (RAW) hazard occurs. It is a part of data dependency.
(ii) Execution of a conditional jump instruction causes a flushing so conditional dependency occurs.
(iii) j^th and j + 1^st instructions require the ALU at the same time causes write-after-read (WAR) hazard.

2 Which of the following statements about relative addressing mode is FALSE ?

As relative address are calculated from absolute address, So relative addressing cannot be faster than absolute addressing.

3 Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor.
1. It must be a trap instruction
2. It must be a privileged instruction
3. An exception can not be allowed to occur during execution of an RFE instruction.

For any exception, while executing RFE, no exception is alllowed (no interrupts). I t is a priveleged instruction, as soon as exception occurs RFE is called (executed).

4 Consider two processors P1 and P2 executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P2 takes 25% less time but incurs 20% more CPI (clock cycles er instruction) as compared to the program running on P1. If the clock frequency of P1 is 1GHz, then the clock frequency of P2 (in GHz) is ...........

1 cycle time for p₁ = 10₁/1GH = 1n.s.
Assume p₁ takes 5 cycles for a program then p₂ takes 20% more, means, 6 cycles.
p₂ Takes 25% less time, means, if p₁ takes 5 n.s, then p₂ takes 3.75 n.s.
Assume p₂ clock frequency is x GHz.
p₂ taken 6 cycles, so 6*10₁/xGH = 3.75, x = 1.6

5 Suppose the functions F and G can be computed in 5 and 3 nanoseconds by functional units U_F and U_G, respectively. Given two instances of U_Fand two instances of U_G , it is required to implement the computation F(G(X_i ) for 1 ≤ i ≤ 10. Ignoring all other delays, the minimum time required to complete this computation is ............. nanoseconds.

There are two functional units each unit get 5 numbers of units to compute on. Suppose computation starts at time 0.
which means G starts at 0 and F starts at 3rd second since G finishes computing first element at third second.
Time at which F ends computing = 3 + 5 * 5 = 28

Computer System Architecture MCQ - Central Processing Unit

Computer System Architecture Central Processing Unit Questions for UGC NET Computer Science

Central Processing Unit MCQ

Central Processing Unit Multiple choice questions

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