Computer System Architecture MCQ - Pipeline and Vector Processing

16 Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is ......

For 6 stages, non-pipelining takes 6 cycles There were 2 stall cycles for pipelining for 25% of the instructions
So pipe line time = [1+(2 25/100)] = 3/2 = 1.5
Speed up = Non– pipeline time/Pipeline time = 6/1.5

17 An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconsd). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage i the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is ..............

18 Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.
P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2 : Four-stage pipeline with stage latencies 1.5 ns, 1.5 ns, 1.5 ns.
P3 : Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4 : Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
Which processor has the highest peak clock frequency?

Peak clock frequency = 1 / Maximum latency
Maximum of latencies is minimum in P3
i.e. P1 : f = 1/2 = 0.5 GHz
P2 : f = 1/1.5 = 0.67 GHz
P4 : f = 1/1.1 GHz
P3 : f = 1/1 GHz = 1
Thus P3 is be the right answer

19 Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clcok speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is .......... .

Speedup = Execution Time Old/Execution Time New Execution Time Old = CPI _Old * Cycle Time_Old
[Here CPI is Cycles Per Instruction] = CPI_Old * Cycle Time Old
= 4 * 1/2.5 Nanoseconds
= 1.6 ns
Since there are no stalls, CPU_new can be assumed 1 on average.
Execution Time New = CPI_new
* Cycle Time_new
= 1 * 1/2
= 0.5
Speedup = 1.6/0.5 = 3.2

20 Consider the following reservation table for a pipeline having three stages S1, S2and S3.

The minimum average latency (MAL) is ............ .

Minimum average latency is 3