Computer System Architecture - Pipeline and Vector Processing
- Option : B
- Explanation : Translations Look aside Buffer can be accessed during effective address calculations.
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- Option : B
- Explanation : Pipelining does not increase the execution time
of a single instruction. It increases the overall
performance by executing instructions in multiple
pipeline stages.
For N=1
Pipelined CPU :
Total time (T1) = (K + (N – 1)) * T = KT
Non-Pipelined CPU :
Total time (T2) = KNT = KT
Considering buffer delays in pipelined CPU,
T1 > = T2
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3. The performance of a pipelined processor suffers if
- Option : D
- Explanation : Pipelining is a method to execute a program
breaking it in several independent sequence of
stages.
In that case pipeline stages can’t have different delays, no dependency among consecutive instructions and sharing of hardware resources should not be there.
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| S1 | S2 | S3 | S4 | |
| I1 : | 1 | 2 | 1 | 2 |
| I2 : | 2 | 1 | 2 | 1 |
| I3 : | 1 | 1 | 2 | 1 |
| I4 : | 2 | 1 | 2 | 1 |
- Option : C
- Explanation :
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- Option : B
- Explanation : Delay is 5 nanosecond/stage.
Total delay in pipeline = 150 + 120 + 160 + 140
= 570
Delay due to stage delay = 15
Total delay = 585
Total time taken = 1000 data item size/585ns
= 165.5 microsecond
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