Pipeline and Vector Processing Q.19

19Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clcok speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is .......... .

Option : A
Explanation : Speedup = Execution Time Old/Execution Time New Execution Time Old = CPI _Old * Cycle Time_Old
[Here CPI is Cycles Per Instruction] = CPI_Old * Cycle Time Old
= 4 * 1/2.5 Nanoseconds
= 1.6 ns
Since there are no stalls, CPU_new can be assumed 1 on average.
Execution Time New = CPI_new
* Cycle Time_new
= 1 * 1/2
= 0.5
Speedup = 1.6/0.5 = 3.2

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