Computer System Architecture MCQ - Pipeline and Vector Processing

11 Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions 11, 12, 13, 14 in stage S1, S2, S3, S4 is shown below :

	S1	S2	S3	S4
I1	2	1	1	1
I2	1	3	2	2
I3	2	1	1	3
I4	1	2	2	2

What is the number of cycles needed to execute the following loop ?
for (i = 1 to 2) {I1; I2; I3; I4;}

1st time for loop required is cycle and again second time 15 cycle
So, total = 30 cycle

12 A 5-stage pipelines processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions ?
Instruction Meaning of Instruction

Clocks

13 Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.

What is the approximate speed up of the pipeline in steady state under ideal conditions when compated to the corresponding non-pipeline implementation?

Pipeline registers overhead is not counted in normal time execution
So the total count will be
5 + 6 + 11 + 8 = 30 [without pipeline]
Now, for pipeline, each stage will be of 11 n-sec (+ 1 n-sec for overhead).
and, in steady state output is produced after every pipeline cycle. Here, in this case 11 n-sec. After adding 1n-sec overhead, We will get 12 n-sec of constant output producing cycle.
dividing 30/12 we get 2.5

14 Register renaming is done in pipelined processors

15 Consider an instruction pipeline with five stages without any branch prediction : Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instruction I1, I2, I3, ........... I12 is execute in the pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

Given: Five stage instruction pipeline Delays for FI, DI, FO, EI and WO are 5, 7, 10, 8, 6 ns resp.
To find: Time needed to execute 12 instruction prog.
Analysis: Since the max. time taken by any stage is 10 ns and additional 1 ns is required for delay of buffer. Therefore total time for an instruction to pass from one stage to another is 11ns. Now instructions are executed as follows:

Now when I₄ is in its execution stage we detect the branch and when I₄ is in WO stage we fetch I₉ so time for execution of instructions from I₁ to I₄ is = 11*5 + (4 – 1)*11 = 88 ns.
And time for execution of instructions from I₉ to I₁₂ is = 11*5 + (4 – 1)*11 = 88 ns. = 88 ns. But we have 11ns when fetching I₉ i.e. I₉ requires only 44 ns additional instead of 55 ns because time for fetching I₉ can be overlap with WO of I₄.
Hence total time is = 88 + 88 – 11 = 165 ns