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Computer System Architecture MCQ - Pipeline and Vector Processing

46 Consider a Direct Mapped Cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24. Which of the following memory blocks will not be in the cache at the end of the sequence?

47 On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500
LOOP : Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the court
If count ! = 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute it it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.
The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DM controller requires 20 clock cycles for initialization and other overhead. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from interrupt driven program based input-output?

Interrupt driven transfer time
= 1 + 1 + 500 * (2 + 2 + 1 + 1 + 1) = 3502
DMA based transfer time = 20 + 500 * 2 = 1020
Speedup = 3502/1020 = 3.4(approx.)

48 The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is .......... .

Size of data count register is 16 bits
Data that can be transferred in one ti
me = 2¹⁶ bytes = 64 kilobytes
File size to be transferred = 29154 kilobytes
So, number of times the DMA controller needs to get the control is 29154/64 = 455.53 (take 456).

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Question:

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions 11, 12, 13, 14 in stage S1, S2, S3, S4 is shown below…

A. 16
B. 23
C. 28
D. 30

Correct answer: D

Explanation:

1st time for loop required is cycle and again second time 15 cycle So, total = 30 cycle

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