Computer System Architecture MCQ - Pipeline and Vector Processing

6 We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time. How much time can be saved using design D2 over design D1 for executing 100 instructions?

Total execution time = (k + n – 1) * maximum clock cycle
Where k = total number of stages and n = total number of instructions
For D1 :
k = 5 and n = 100
Maximum clock cycle = 4ns
Total execution time = (5 + 100 – 1) * 4 = 416
For D2 :
k = 8 and n = 100
Each clock cycle = 2ns Total execution time = (8 + 100 – 1) * 2 = 214
Thus, time saved using D2 over D1
= 416 – 214
= 202

7 A nonpipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec, respectively. The delay of the latches is 0.5 nsec. The speedup of the pipeline processor for a large number of instructions is

For non pipelined system time required
= 2.5 + 1.5 + 2.0 + 1.5 + 2.5 = 10
for pipelined system
= Max (stage delay) + Max(Latch delay)
= 2.5 + 0.5 = 3.0
speedup = time in non-pipelined system/time in pipelined system
= 10/3 = 3.33