Computer System Architecture - Pipeline and Vector Processing
- Option : B
- Explanation : Total execution time = (k + n – 1) * maximum
clock cycle
Where k = total number of stages and n = total number of instructions
For D1 :
k = 5 and n = 100
Maximum clock cycle = 4ns
Total execution time = (5 + 100 – 1) * 4 = 416
For D2 :
k = 8 and n = 100
Each clock cycle = 2ns Total execution time = (8 + 100 – 1) * 2 = 214
Thus, time saved using D2 over D1
= 416 – 214
= 202
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- Option : C
- Explanation : For non pipelined system time required
= 2.5 + 1.5 + 2.0 + 1.5 + 2.5 = 10
for pipelined system
= Max (stage delay) + Max(Latch delay)
= 2.5 + 0.5 = 3.0
speedup = time in non-pipelined system/time in pipelined system
= 10/3 = 3.33
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- Option : A
- Explanation : In pipelined processor bypassing can handle all RAW hazards and register remaining can eliminate all register carried WAR hazard.
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Delayed branching can help in the handling of control hazardous
- Option : B
- Explanation : For all delayed conditional branch instructions the first instruction in the fall through path is executed
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Delayed branching can help in the handling of control hazardous
- Option : B
- Explanation : In delay slot I2 will be there
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