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Pipeline and Vector Processing Q.7

0. A nonpipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec, respectively. The delay of the latches is 0.5 nsec. The speedup of the pipeline processor for a large number of instructions is

  • Option : C
  • Explanation : For non pipelined system time required
    = 2.5 + 1.5 + 2.0 + 1.5 + 2.5 = 10
    for pipelined system
    = Max (stage delay) + Max(Latch delay)
    = 2.5 + 0.5 = 3.0
    speedup = time in non-pipelined system/time in pipelined system
    = 10/3 = 3.33
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