Pipeline and Vector Processing Q.10

Delayed branching can help in the handling of control hazardous

10The following code is to run on a pipelines processor with one branch delay slot
I1 : ADDR2 ⇽ R7 + R8
I2 : SIN R4 ⇽ R5 – R6x
I3 : ADD R1 ⇽ R2 + R3
I4 : STORE Memory [R4] ⇽ R1
BRANCH to Label if R1 == 0
Which of the instruction 11, 12, 13 or 14 can legitimately occupy the delay slot without any other program modification?

Option : B
Explanation : In delay slot I2 will be there

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