Computer System Architecture MCQ - Pipeline and Vector Processing

31 Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

It depends on what kind of CPU.

32 A CPU generally handles an interrupt by executing an interrupt service routine

A CPU generally handles an interrupt by executing ISR by checking the interrupt register after finishing execution of the current instruction.

33 For the daisy chain scheme of connecting I/O devices, which of the following statements is true?

Daisy Chain Scheme. When device A has a cable that plugs into device B has a cable that plugs into device C and device C plugs into a port on the computer, this arrangement is called a Daisy Chain. It usually operates as a bus.

34 A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 usec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating under program controlled mode?

If overhead of a single byte transfer with interface mode is 4 ￫ sec, then actual data transfer can be 250000.
Actually transfer take place at the rate ￫ 10000
Now 25 is the minimum performance gain.

35 Consider the following processor design characteristics :
I. Register-to-register arithmetic operations only.
II. Fixed-length instruction format.
III. Hardwired control unit.
Which of the characteristics above are used in the design of a RISC processor ?

RISC processor characteristics:
1. It supports mode registers, so ALU operations are performed only on a register data.
2. It support fixed length instructions.
3. It uses hard-wired control unit.