Computer System Architecture - Pipeline and Vector Processing
- A
Neither vectored interrupt nor multiple interrupting devices are possible
- B
Vectored interrupts are not possible but multiple interrupting devices are possible
- C
Vectored interrupts and multiple interrupting devices are both possible
- D
Vectored interrupt is possible but multiple interrupting devices are not possible.
32. A CPU generally handles an interrupt by executing an interrupt service routine
- Option : C
- Explanation : A CPU generally handles an interrupt by executing ISR by checking the interrupt register after finishing execution of the current instruction.
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33. For the daisy chain scheme of connecting I/O devices, which of the following statements is true?
- Option : A
- Explanation : Daisy Chain Scheme. When device A has a cable that plugs into device B has a cable that plugs into device C and device C plugs into a port on the computer, this arrangement is called a Daisy Chain. It usually operates as a bus.
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- Option : B
- Explanation : If overhead of a single byte transfer with interface
mode is 4 ï¿« sec, then actual data transfer can
be 250000.
Actually transfer take place at the rate ï¿« 10000
Now 25 is the minimum performance gain.
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- Option : D
- Explanation : RISC processor characteristics:
1. It supports mode registers, so ALU operations are performed only on a register data.
2. It support fixed length instructions.
3. It uses hard-wired control unit.
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