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Computer System Architecture - Pipeline and Vector Processing

Avatto > > UGC NET COMPUTER SCIENCE > > PRACTICE QUESTIONS > > Computer System Architecture > > Pipeline and Vector Processing

36. The main differences(s) between a CISC and A RISC processor is/are that a RISC processor typically

  • Option : D
  • Explanation : All statements are true.
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37. Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/ O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O ?

  • Option : A
  • Explanation : We have two regestion limit and base. So, when we refer memory location which is not in range provided by these two regestor is always cause OS to interface.
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38. The data transfer between memory and I/O devices using programmed I/O is faster than interrupt driven I/O.

  • Option : B
  • Explanation : The data transfer between memory and I /O devices using interrupt driven I/O is faster than programmed I/O.
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39. I/O redirection

  • Option : B
  • Explanation : I/O redirection can be employed to use an existing file as input file for a program.
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40. Which of the following DNA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?

  • Option : C
  • Explanation : In block transfer the entire block of data is transferred then only CPU again becomes the bus master and in vectored Interrupts I/o device along with interrupts send vector address of Interrupt Service routine which guides CPU to execute for a specific I/O device.
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Pipeline and Vector Processing