Avatto > UGC NET COMPUTER SCIENCE > PRACTICE QUESTIONS > Computer System Architecture > Pipeline and Vector Processing

Computer System Architecture MCQ - Pipeline and Vector Processing

36 The main differences(s) between a CISC and A RISC processor is/are that a RISC processor typically

All statements are true.

37 Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/ O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O ?

We have two regestion limit and base. So, when we refer memory location which is not in range provided by these two regestor is always cause OS to interface.

38 The data transfer between memory and I/O devices using programmed I/O is faster than interrupt driven I/O.

The data transfer between memory and I /O devices using interrupt driven I/O is faster than programmed I/O.

39 I/O redirection

I/O redirection can be employed to use an existing file as input file for a program.

40 Which of the following DNA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?

In block transfer the entire block of data is transferred then only CPU again becomes the bus master and in vectored Interrupts I/o device along with interrupts send vector address of Interrupt Service routine which guides CPU to execute for a specific I/O device.

Your Progress

0%

Start Practising!

You've answered 0 of 48 questions in this topic.

Practice Spotlight

Build momentum in Pipeline and Vector Processing

Start with a short question set, review every explanation, and revisit difficult questions before moving ahead.

Day 4 / 10

Global Spotlight

Build Your First Streak

Complete one short Pipeline and Vector Processing session today, then return tomorrow. Consistency matters more than a long first session.

Day 7 / 10

Question Spotlight

Question:

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions 11, 12, 13, 14 in stage S1, S2, S3, S4 is shown below…

A. 16
B. 23
C. 28
D. 30

Correct answer: D

Explanation:

1st time for loop required is cycle and again second time 15 cycle So, total = 30 cycle

Click to view the complete question details

Day 4 / 10 Open this question

Community Insight

Based on 47 saved attempts

Most Attempted TopicRegister Transfer and Micro-operations
Most Challenging TopicDigital Logic Circuits - Combinational Circuits
Average Accuracy96%

Featured Question

(Based on recent community answers)

Q. #25491New

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions…

Try This Question →

This Week's Challenge

Complete 20 questions and set the community benchmark!

0 / 20 Start Challenge →

Why Practice with Avatto?

High Quality MCQsExam-focused questions with accurate answers

Detailed ExplanationsStep-by-step explanations to enhance learning

Latest Exam PatternBased on updated syllabus and pattern

Performance AnalyticsTrack performance and improve weak areas

100% Free PracticePractice unlimited questions for free

Forgot your password?

I agree with the Terms.