Central Processing Unit Q.11

0. A 5 stage pipelined CPU has the following sequence of stages
IF - Instruction fetch from instruction memory.
RD - Instruction decode and register read,
EX - Execute : ALU operation for data and address computation.
MA - Data memory access – for write access the register read at RD stage it used,
WB - Register write back.
Consider the following sequence of instructions :
I₁ : L RO, Loc 1; RO ⇐ M[Loc1]
I₂ : A RO, RO; RO ⇐ RO + RO
I₃ : A R2, RO, R2 ⇐R2 – RO
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I₁?

Answer
Comment
Array

Option : B
Explanation : Clock Cycles

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