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Central Processing Unit Q.31

0. Consider a three word machine instruction ADD A[R0], @ B
The first operand (destination) “a [RO]” uses indexed addressing mode with RO as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is

  • Option : B
  • Explanation : In Indexed addressing mode, the base address is already in the instruction i.e A and to fetch the index data from R0 no memory access is required because it’s a register So to fetch the operand only 1 memory cycle i s required. Indirect Addressing mode requires 2 memory cycles only
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