Computer System Architecture MCQ - Central Processing Unit

46 Assume that EA = (X) + is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = –(X) is the effective address equal to the contents of location X, with x decremented by one word length before the effective address is calculated; EA = (X)– is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination  source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

ADD (X)– , (X)

47 The program below uses six temporary variable a, b, c, d, e, f.
a = 1
b = 10
c = 20
d = a + b
e = c + d
f = c + e
b = c + e
e = b + f
d = 5 + e
return d + f
Assuming that all operations take their operands from registers, what is the minimum number of registers needed to execute this program without spilling

a = 1
b = 10 Let a is in Accumulator than for b and c we want c = 20 Register than 2 registers want till now 1 for b and 1 for c
d = a + b N ow d = a + b can be stored in Accumulator because we don’t want a again
e = c + d. Now for f we wan’t next, one register because we wan’t c & e again
f = c + e
b = c + e. Now at b = c + e we can store value in register b already, so we don’t want another
e = b + f. Now at e = b + f we can store it in 0 register of b because we don’t want another
d = 5 + e Now at d = 5 + e we can store it in d because we don’t want e again
than we can say only 3 registers we want.

48 Consider a hypothetical processor with a instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

Here 20 will act as base and content of R2 will be index

49 For computers based on three-address instruction formats, each address field can be used to specify which of the following :
S1 : A memory operand
S2 : A processor register
S3 : An implied accumulator register

In Three address instruction format , each operand specifies either a memory address or a register.

50 Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)16 and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)16. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:
Store the current value of PC i the stack.
Store the vale of PSW register i the stack.
Load the starting address of the subroutine in PC. the content of PC just before the fetch of a CALL instruction is (5FAO)16. After execution of the CALL instruction, the value of the stack pointer is

The current value of Stack pointer is (016E)₁₆ The value of SP after following operations is asked in question
(1) Store the current value of PC in the stack. This operation increments SP by 2 bytes as size of PC is given 2 bytes in question. So (016E)₁₆ + 2 = (0170)₁₆
(2) Store the value of PSW register in the stack. This operation also increments SP by 2 bytes as size of PSW is also given 2 bytes.
So (0170)₁₆ + 2 = (0172)₁₆
(3) Load the starting address of the subroutine in PC.
The Load operation doesn't change SP. So new value of SP is (0172)₁₆