Classical

Digital Logic - Sequential Circuits

41:  

 If a single clock pulse is applied, and following  inputs are given to the J-K flip flop,   then device will
JK flip flop

 

A.

toggle

B.

set

C.

reset

D.

not change states

 
 

Option: D

Explanation :


42:  

 The logic circuit shown below  operates as a : 
flip flop

 

A.

4-bit asynchronous counter

B.

4-bit synchronous counter

C.

BCD counter

D.

Serial-In Serial-Out shift register

 
 

Option: A

Explanation :


43:  

If in a shift resistor Q0 is fed back to input  the resulting counter is

A.

Twisted ring with N : 1 scale

B.

Ring counter with N : 1 scale

C.

Twisted ring with 2N : 1 scale

D.

Ring counter with 2 N : 1 scale

 
 

Option: C

Explanation :


44:  

 For the initial state of 000, the function performed bt the arrangement of the J-K flip-flop in the given figure is
j k flip flop

A.

shift register

B.

mod-3 counter

C.

mod-6 counter

D.

mod-2 counter

 
 

Option: C

Explanation :


45:  

 The circuit shown in the figure given below
oscillating circuit

A.

is an oscillating circuit and its output is a square wave

B.

is one whose output remains stable in ' 1 ' state

C.

is one having output remains stable ' 0 ' state

D.

having a single pulse of 3 times propagation delay

 
 

Option: A

Explanation :




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