Digital Logic - Sequential Circuits

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36:   A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the 'toggle' mode. The frequency of the signal at the output will be

A.	1 MHz
B.	2 MHz
C.	6 MHz
D.	8 MHz
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	Option: D Explanation : Click on Discuss to view users comments. Write your comments here: Updating your Comments.. Updating your Comments.. '>

37:   The master slave JK lip-flop is effectively a combination of

A.	A SR flip-flop and a T flip-flop
B.	An SR flip-lfop and a D flip-flop
C.	A T flip-flop and a D flip-flop
D.	Two D flip-flops
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	Option: A Explanation : Click on Discuss to view users comments. Write your comments here: Updating your Comments.. Updating your Comments..

38:   It is difficult to design asynhronous sequential circuit because

A.	External clock is to be provided
B.	It is more complex
C.	Both (a) and (b)
D.	Generally they involve stability problem
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	Option: D Explanation : Click on Discuss to view users comments. Write your comments here: Updating your Comments.. Updating your Comments..

39:   A stable multivibrator is used as

A.	Comparator circuit
B.	Demultiplexer
C.	Frequency to voltage converter
D.	Voltage to frequency converter
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	Option: A Explanation : Click on Discuss to view users comments. Write your comments here: Updating your Comments.. Updating your Comments..

40:   How many flip-flop are needed to divide the input frequency by 64 ?

A.	2
B.	5
C.	6
D.	8
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	Option: C Explanation : Click on Discuss to view users comments. Write your comments here: Updating your Comments.. Updating your Comments..

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