Classical

Digital Logic - Sequential Circuits

36:   If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by
A. nT sec
B. (n-1)T sec
C. n/T sec
D. (2n+1)T sec
 
 

Option: B

Explanation :

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37:   Register is a
A. set of capacitor used to register input instructions in a digital computer
B. set to paper tapes and cards put in a file
C. temporary storage unit within the CPU having dedicated or general purpose use
D. part of the main memory
 
 

Option: C

Explanation :


38:   The number of flip-flops required in a decade counter is
A. 3
B. 4
C. 8
D. 10
 
 

Option: B

Explanation :


39:  

The correct state sequence of the circuit  with initial state Q0=1, Q1Q= 0. The state of the circuit is given by the value 4Q2+ 2 Q1+Q0.
xor flip flop

 

A.

1, 3, 4, 6, 7, 5, 2

B.

1, 2, 5, 3, 7, 6, 4

C.

1, 2, 7, 3, 5, 6, 4

D.

1, 6, 5, 7, 2, 3, 4

 
 

Option: D

Explanation :


40:  

What is the modulo (number of pressing states) of  the counter shown below
shift register

A.

3

B.

6

C.

8

D.

Modulo cannot be determined from the circuit

 
 

Option: A

Explanation :




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