Classical

Digital Logic - Sequential Circuits

46:  

 In the circuit shown below  the input data is fixed at a LOW level and the output values are as shown in the figure. The number of lock pulses required to give an output of Φ Φ Φ Φ is
shift register

A.

2

B.

3

C.

4

D.

5

 
 

Option: A

Explanation :


47:  

 In the figure given below  if Initially all flip-flops are cleared then how many clock pulses have to be applied to the system before the output from FF3 becomes a HIGH level?
flip flop

A.

2

B.

4

C.

6

D.

8

 
 

Option: B

Explanation :


48:  

The inputs of the J-K flip-flop,  are  PRESET = CLEAR = 1 : J = K = 0 
If  a single closk pulse is applied, then device will

j-k flip flop

A.

toggle

B.

set

C.

reset

D.

not change states

 
 

Option: D

Explanation :


49:  

 The logic circuit shown below is a 32-bit
Binary up counter

A.

shift register

B.

asynchronous binary up counter

C.

asynchronous binary down counter

D.

synchronous binary up counter

 
 

Option: D

Explanation :




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