Digital Logic - Sequential Circuits

56:  

 For the initial state of 000, the function performed bt the arrangement of the J-K flip-flop in the given figure is
j k flip flop

A.

shift register

B.

mod-3 counter

C.

mod-6 counter

D.

mod-2 counter

 
 

Option: C

Explanation :

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57:  

 The circuit shown in the figure given below
oscillating circuit

A.

is an oscillating circuit and its output is a square wave

B.

is one whose output remains stable in ' 1 ' state

C.

is one having output remains stable ' 0 ' state

D.

having a single pulse of 3 times propagation delay

 
 

Option: A

Explanation :

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58:  

 In the circuit shown below  the input data is fixed at a LOW level and the output values are as shown in the figure. The number of lock pulses required to give an output of Φ Φ Φ Φ is
shift register

A.

2

B.

3

C.

4

D.

5

 
 

Option: A

Explanation :

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59:  

 In the figure given below  if Initially all flip-flops are cleared then how many clock pulses have to be applied to the system before the output from FF3 becomes a HIGH level?
flip flop

A.

2

B.

4

C.

6

D.

8

 
 

Option: B

Explanation :

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60:  

The inputs of the J-K flip-flop,  are  PRESET = CLEAR = 1 : J = K = 0 
If  a single closk pulse is applied, then device will

j-k flip flop

A.

toggle

B.

set

C.

reset

D.

not change states

 
 

Option: D

Explanation :

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