Classical

Digital Logic - Sequential Circuits

26:   It is difficult to design asynhronous sequential circuit because
A. External clock is to be provided
B. It is more complex
C. Both (a) and (b)
D. Generally they involve stability problem
 
 

Option: D

Explanation :

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27:   A stable multivibrator is used as
A. Comparator circuit
B. Demultiplexer
C. Frequency to voltage converter
D. Voltage to frequency converter
 
 

Option: A

Explanation :

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28:   How many flip-flop are needed to divide the input frequency by 64 ?
A. 2
B. 5
C. 6
D. 8
 
 

Option: C

Explanation :

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29:   In a ripple counter using edge triggered JK flfp-flops, the pulse input is applied to the
A. clock input of all flip-flops
B. clock input of one flip-flops
C. J and K inputs of all flip-flops
D. J and K inputs of one flip-flop
 
 

Option: D

Explanation :

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30:   The number of clock pulses needed to shift one byte of data from input to the output of a 4-bit shift register is
A. 10
B. 12
C. 16
D. 32
 
 

Option: C

Explanation :

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