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Computer System Architecture - Memory Hierarchy

Avatto > > UGC NET COMPUTER SCIENCE > > PRACTICE QUESTIONS > > Computer System Architecture > > Memory Hierarchy

81. Consider a machine with a byte addressable main memory of 232 divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is ................ .

  • Option : A
  • Explanation : Total address space = 32 bit
    offset bit (B) = 5 bit
    No. of bit to represent line no (L) = 9.
    Tag bit + B + L = 32
    = X + 5 + 9 = 32
    = X = 18
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82. In a two-level virtual memory, the memory access time for main memory, tA1 = 10–8 sec, and the memory, tag = 10–3 sec. What must be the hit ratio, H such that the access efficiency is within 80 percent of its maximum value.

  • Option : B
  • Explanation : Main Memory access time = 10–8 sec = (ta1)
    Secondary Memo. access time = 10–3 sec = (ta2)
    Access efficiency (n) = 80% = 0.8
    Average Access time
    tavg = n * ta1 = 0.8 × 10–3 sec
    for Hit ratio H
    tavg = H * ta1 + (1– H) * ta2
    0.8 × 10–3 = H * 10–8 + (1 – H) * 10–3
    0.8 = H × 10–5 + (1 – H)
    H(1 – 10–5) = 0.2
    H = 0.2/(1-10–5)
    = 0.200002
    = 20%
    H = 20%
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83. Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals, During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time.
The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ........... .

  • Option : A
  • Explanation : Each write request, the bus is occupied for 100 n.s
    Storing of data requires 100 n.s.
    In 100 n.s. – 1 store
    100/106 n.s. = 1 store
    1 m.s. = 106/100 stores =
    10000 stores.
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84. A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ................ bits.

  • Option : D
  • Explanation : 230+2/2 = 231
    So 31 bits required.
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85. A 32-bit wide main memory unit with a capacity of 1 GB is built using 256 M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 214. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is ............

  • Option : C
  • Explanation : Given, total number of rows is 214 and time taken to perform one refresh operation is 50 nanoseconds.
    So, total time taken to perform refresh operation
    = 214 * 50 nanoseconds
    = 819200 nanoseconds
    = 0.819200 milliseconds.
    But refresh period is 2 milliseconds.
    So, time spent in refresh period in percentage
    = (0.819200 milliseconds) / (2 milliseconds)
    = 0.4096 = 40.96%
    Hence, time spent in read/write operation
    = 100% – 40.96% = 59.04% = 59
    (in percentage and rounded to the closet integer).
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