Computer System Architecture - Memory Hierarchy
A computer has a 256 Kbytes, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.
76. The size of the cache tag directory is
- Option : A
- Explanation : Tag is 16 bit, 2 bit valid, 1 modified, 1 replace
Total bits for tag entry = 16 + 2 + 1 + 1 = 20
Size of tag array = 20 * no. of blocks
= 160 K bits.
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- Option : A
- Explanation : Miss ratio = (Cache miss)/(No. of request)
= n/N
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- Option : D
- Explanation : When a cache block size is smaller, it could accommodate more number of blocks, it improves the hit ratio for cache, so the miss penalty for cache will be lowered.
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- Option : A
- Explanation : Time taken by the original design
= (2n * 2t) + (3n * t)
= 7nt
Time taken by enhanced design
= (2n * 2t /1.2) + (3n * t/1.1)
= 6.06 nt
Speed up = 7 nt/6.06 nt
= 1.155
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- Option : A
- Explanation : Type of mapping is direct map; for this direct map, 10 bits are required in its Tag. It is updated to 16 way set Associative map then new tag field size = 10 + log2 16 = 14 bits, because for k way set associative map design, log2 k bits are additionally required to the number of bits in tag field for Direct map design.
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