Avatto > UGC NET COMPUTER SCIENCE > PRACTICE QUESTIONS > Computer System Architecture > Memory Hierarchy

Computer System Architecture MCQ - Memory Hierarchy

86 Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.

Statement is true, main memory transfer the data in the form of block to cache and cache transfer the data in the form of words, so it enables the interleaved main memory unit to operate unit at maximum speed

87 A 4-ways set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is ......................... .

Your Progress

0%

Start Practising!

You've answered 0 of 87 questions in this topic.

Practice Spotlight

Build momentum in Memory Hierarchy

Start with a short question set, review every explanation, and revisit difficult questions before moving ahead.

Day 4 / 10

Global Spotlight

Build Your First Streak

Complete one short Memory Hierarchy session today, then return tomorrow. Consistency matters more than a long first session.

Day 7 / 10

Question Spotlight

Question:

An 8KB direct-mapped write back cache is organized as multiple blocks, each of size 32 bytes. The processor generates 32 bit addresses. The cache controller maintains the tag…

A. 4864 bits
B. 6144 bits
C. 6656 bits
D. 5376 bits

Correct answer: D

Click to view the complete question details

Day 4 / 10 Open this question

Community Insight

Based on 47 saved attempts

Most Attempted TopicRegister Transfer and Micro-operations
Most Challenging TopicDigital Logic Circuits - Combinational Circuits
Average Accuracy96%