Computer System Architecture MCQ - Digital Logic Circuits - Combinational Circuits
63
In the following question, match each of the items A, B and C on the left with an approximation item on the right
| A. Shift register can be used | 1. for code conversion |
| B. A multiplexer can be used | 2. to generate memory slip to select |
| C. A decoder can be used | 3. for parallel to serial conversion |
| 4. as many to one switch | |
| 5. for analog to digital conversion |
64
A full-adder is a logic circuit which can add two single order bits plus a carry in from a previous adder. Its incomplete truth table is given in the table below. The missing entry in the outputs for SUM and CARRY out are
Input | Outputs | ||||
A | A | B | Cin | Sum | CarryOUT |
0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 1 | 1 | 0 |
0 | 0 | 1 | 0 | 1 | 0 |
0 | 0 | 1 | 1 | 0 | 1 |
1 | 1 | 0 | 0 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 |
1 | 1 | 1 | 0 | 0 | 1 |
1 | 1 | 1 | 1 | ? | ? |
