Computer System Architecture - Digital Logic Circuits - Combinational Circuits
62. The full adder adds the Kth bits of two numbers to the
- Option : C
- Explanation :
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| A. Shift register can be used | 1. for code conversion |
| B. A multiplexer can be used | 2. to generate memory slip to select |
| C. A decoder can be used | 3. for parallel to serial conversion |
| 4. as many to one switch | |
| 5. for analog to digital conversion |
- Option : B
- Explanation :
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Input | Outputs | ||||
A | A | B | Cin | Sum | CarryOUT |
0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 1 | 1 | 0 |
0 | 0 | 1 | 0 | 1 | 0 |
0 | 0 | 1 | 1 | 0 | 1 |
1 | 1 | 0 | 0 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 |
1 | 1 | 1 | 0 | 0 | 1 |
1 | 1 | 1 | 1 | ? | ? |
- Option : D
- Explanation :
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65. Extremely low power dissipation and low cost per gate can be achieved in:
- Option : B
- Explanation :
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