Computer System Architecture - Central Processing Unit
Consider the following data path of a CPU
The, ALU, the bus and all the registers in the data
path are of identical size. All operations including
incrementation of the PC and the GPRs are to be
carried out in the ALU. Two clock cylces are needed
for memory read operation – the first one for loading
address in the MAR and the next one for loading data
from the memory but into the MDR.
Consider the following data path of a CPU
The, ALU, the bus and all the registers in the data
path are of identical size. All operations including
incrementation of the PC and the GPRs are to be
carried out in the ALU. Two clock cylces are needed
for memory read operation – the first one for loading
address in the MAR and the next one for loading data
from the memory but into the MDR.
Which of the following below is TRUE after the program is executed ?
- Option : C
- Explanation : In the 3rd stage of pipeline, there will be 2 stall
cycles i.e. 2 delay slots.
Total number of instructions = 109
= (0.2 * (2 + 1) + 0.8 * 1) * 10^9
= 1.4 sec
