Classical

Digital Logic - Combinational Circuits

6:   Odd parity of word can beconveniently tested by
A. OR gate
B. AND gate
C. NOR gate
D. XOR gate
 
 

Option: D

Explanation :


7:  

Identify the logic function performed by the circuit shown in the given figure
logic-circuit

A.

Exclusive OR

B.

Exclusive NOR

C.

NAND

D.

NOR

 
 

Option: B

Explanation :


8:   Which one of the following will give the sum of full adders as output ?
A. Three point majority circuit
B. Three bit parity checker
C. Three bit comparator
D. Three bit counter
 
 

Option: D

Explanation :


9:  

The number of full and half-adders required to add 16-bit numbers is

A.

8 half-adders, 8 full-adders

B.

1 half-adder, 15 full-adders

C.

16 half-adders, 0 full-adders

D.

4 half-adders, 12 full-adders

 
 

Option: B

Explanation :

The one half-adder can add the least significant bit of the two numbers. Full adders are required to add the remaining 15 bits as they all involve adding carries.


10:   The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called
A. Rise time
B. Decay time
C. Binary level transition period
D. Propagation delay
 
 

Option: B

Explanation :




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Syllabus covered in this section is-

  • Logic functions, Minimization,
  • Design and synthesis of combinational and sequential circuits
  • Number representation and computer arithmetic (fixed and floating point)
  • Propositional (Boolean) Logic
  • Satisfiability and Tautology
  • Logic Families: TTL, ECL and C-MOS gates.
  • Boolean algebra and Minimization of Boolean functions
  • Flip-flops-types, race condition and comparison.
  • Design of combinational and sequential Circuits
  • Representation of Integers: Octal, Hex. Decimal and Binary.
  •  2's complement and 1 's complement arithmetic
  • Floating point representation.

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