# Digital Logic - Combinational Circuits

1:

In which of the following gates, the output is 1, if and only if at least one input is 1?

 A. NOR B. AND C. OR D. NAND Answer Report Discuss Option: C Explanation : In OR gate  we need atleast one bit to be equal to 1 to generate the output as 1 because OR means  any of the condition out of two is equal to 1  which means  if atleast one input is 1 then it shows output as 1 . Number of 1's in input may be more than one but the output will always be 1 in OR gate. So the answer is 'C'. Click on Discuss to view users comments. Write your comments here:
2:   The time required for a gate or inverter to change its state is called
 A. Rise time B. Decay time C. Propagation time D. Charging time Answer Report Discuss Option: C Explanation : Click on Discuss to view users comments. aruna said: (11:13pm on Saturday 7th September 2013) propagation time Write your comments here:
3:   The time required for a pulse to change from 10 to 90 percent of its maximum value is called
 A. Rise time B. Decay time C. Propagation time D. Operating speed Answer Report Discuss Option: A Explanation : Click on Discuss to view users comments. Write your comments here:
4:   The maximum frequency at which digital data can be applied to gate is caled
 A. Operating speed B. Propagation speed C. Binary level transaction period D. Charging time Answer Report Discuss Option: A Explanation : Click on Discuss to view users comments. Write your comments here:
5:

What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?

 A. one B. two C. three D. four Answer Report Discuss Option: C Explanation : Y=A+B. This is the equation of OR gate. We require 3 NAND gates to create  OR gate.  We can also write After 1st NAND operation Y = (A AND B)'  Y=  A'  + B'  (Demorgan's Law) After 2nd NAND operation Y= ( A'  + B')' Y=  A . B  (Demorgan's Law) After 3rd  NAND operation Y= ( A . B )' Y=  A' +  B '  (Demorgan's Law) So we need 3 NAND gates. Click on Discuss to view users comments. meena vinay said: (12:45pm on Tuesday 21st April 2015) the ouput after ist NAND and third NAND is same.So the answer is not correct Gitanjali said: (1:43pm on Saturday 26th November 2016) After first nand gate as well we are getting or answer .So the answer shd be after one nand gate prathap said: (10:12pm on Wednesday 21st December 2016) when we see the implementation of OR gate using NAND gate it is clearly saying that the minimum number of 2 input required are 3. Shahroze Arslan said: (5:35am on Wednesday 9th May 2018) a simple way to check this is through truth tableThe truth table of one OR gate (accepting two inputs minimum) and one NAND (accepting two inputs minimum) is same Write your comments here:

Syllabus covered in this section is-

• Logic functions, Minimization,
• Design and synthesis of combinational and sequential circuits
• Number representation and computer arithmetic (fixed and floating point)
• Propositional (Boolean) Logic
• Satisfiability and Tautology
• Logic Families: TTL, ECL and C-MOS gates.
• Boolean algebra and Minimization of Boolean functions
• Flip-flops-types, race condition and comparison.
• Design of combinational and sequential Circuits
• Representation of Integers: Octal, Hex. Decimal and Binary.
•  2's complement and 1 's complement arithmetic
• Floating point representation.

This Section covers Digital Logic Questions Answers .

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