Classical

Digital Logic - Combinational Circuits

46:  

 Which one of the following logic expression is incorrect?

A.

1 ⊕ 0 = 1

B.

1 ⊕ 1 ⊕ 0 = 1

C.

1 ⊕ 1 ⊕ 1 = 1 

D.

1 ⊕ 1 = 0

 
 

Option: B

Explanation :

Click on Discuss to view users comments.

Write your comments here:



47:  

 The circuit shown in the figure is equivalent to?
Question logic circuit

A.

answer option a

B.

answer option b

C.

answer option c

D.

answer option d

 
 

Option: B

Explanation :

Click on Discuss to view users comments.

wdw said: (11:20pm on Monday 6th January 2014)
Please Explain how ?

Write your comments here:



48:  

The black box in the following figure consists of a minimum complexity circuit that uses only AND,OR and NOT gates. The function f (x,y,z) = 1 whenever x , y are different and 0 otherwise. In addition the 3 inputs x,y,z are never all the same value. Which of the following equation lead to the correct design for the minimum complexity circuit?
black box

A.

x'y + xy' 

B.

x + y'z

C.

x'y'z' + xy'z

D.

xy + y'z + z'

 
 

Option: A

Explanation :

Click on Discuss to view users comments.

rehan said: (1:41am on Sunday 1st March 2015)
A part not contain the value of Z so how it full fill the function ?????????

Write your comments here:



49:  

 If A ⊕ B = C, then

A.

A ⊕ C = B

B.

B ⊕ C = A

C.

A ⊕ B ⊕ C = 0

D.

Both (a) & (b)

 
 

Option: D

Explanation :

Mathematically, XOR is both associative and commutative ie.
 

If C = A  XOR  B then B = C  XOR  A or  B = A  XOR  C and
 

and A = B  XOR C   A = C  XOR  B

Click on Discuss to view users comments.

bikash said: (11:05am on Wednesday 4th September 2013)
Option C is also correct
bikash said: (11:05am on Wednesday 4th September 2013)
Option C is also correct

Write your comments here:



50:  

 To make the following circuit a tautology ? marked box should be  
nand gate output

 

A.

OR gate

B.

AND gate

C.

NAND gate

D.

EX-OR GATE

 
 

Option: C

Explanation :

The output f = (x+x')+(y+y').

Starting derivation using 'f'.

-->(x+x')+(y+y')

-->(x+y)+(x'+y')

-->(Already a known Input)+(x'+y')

So, the unknown input is (x'+y'). This can be made by :-

x and y fed into a NOT gate and then AND gate to become (x'+y').

So the answer is NAND gate.

Click on Discuss to view users comments.

nishanthi said: (11:34pm on Saturday 27th July 2013)
please help me how to get this answer?
swetha k said: (3:02am on Tuesday 6th October 2015)
it should be XOR isn't it??

Write your comments here:





Suggest an improvement