Computer System Architecture - Digital Logic Circuits - Sequential Circuit

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6. A mod-2 counter followed by a mod-5 counter is

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7. What is the maximum counting speed of a 4-bit binary counter which is composed of flip-flops with a propagation delay of 25 ns ?

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8. A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now

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9. Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is applied at the input S,then the output

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10. The output of a sequential circuit depends on

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