info@avatto.com
+91-9920808017
16. A pulse train can be delayed by a finite number of clock periods using
A serial-in serial-out shift register
A serial-in parallel-out shift register
Both (a) and (b)
A parallel-in parallel-out shift register
Your email address will not be published. Required fields are marked *
Report
Name
Email
Website
Save my name, email, and website in this browser for the next time I comment.
Comment
17. How many illegitimate states has synchronous mod-6 counter ?
3
2
1
6
18. A 2 bit binary multiplier can be implemented using
2 input ANDs only
2 input XORs and 4 input AND gates only
2 input NORs and one XNOR gate
NOR gates and shift registers
19. A ring counter is same as
up-down counter
parallel-counter
shift register
Ripple carry Counter
20. The dynamic hazard problem occurs in
Combinational circuit alone
Sequential circuit only
None of these
Login with Facebook
Login with Google
Forgot your password?
Lost your password? Please enter your email address. You will receive mail with link to set new password.
Back to login