Computer System Architecture - Digital Logic Circuits - Sequential Circuit

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56. The circuit shown in the figure given below

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Option : A
Explanation :

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57. In the circuit shown below the input data is fixed at a LOW level and the output values are as shown in the figure. The number of lock pulses required to give an output of Φ Φ Φ Φ is

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Option : A
Explanation :

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58. In the figure given below if Initially all flip-flops are cleared then how many clock pulses have to be applied to the system before the output from FF3 becomes a HIGH level?

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Option : B
Explanation :

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59. The inputs of the J-K flip-flop, are PRESET = CLEAR = 1 : J = K = 0 If a single clock pulse is applied, then device will

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Option : D
Explanation :

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60. The logic circuit shown below is a 32-bit

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Option : D
Explanation :

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Digital Logic Circuits - Sequential Circuit

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