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Computer System Architecture - Digital Logic Circuits - Sequential Circuit

Avatto > > UGC NET COMPUTER SCIENCE > > PRACTICE QUESTIONS > > Computer System Architecture > > Digital Logic Circuits - Sequential Circuit

46. If the input J is connected through K input of J-K, then flip-flop will behave as a

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47. If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by

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48. Register is a

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49. The number of flip-flops required in a decade counter is

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50. The correct state sequence of the circuit  with initial state Q0=1, Q1Q2 = 0. The state of the circuit is given by the value 4Q2+ 2 Q1+Q0. The correct state sequence of the circuit with initial state Q0=1, Q1Q2 = 0. The state of the circuit is given by the value 4Q2+ 2 Q1+Q0.

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Digital Logic Circuits - Sequential Circuit