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Computer System Architecture - Central Processing Unit

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36. Horizontal microprogramming

  • Option : D
  • Explanation : All statements are true.
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37. An instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as follows :
Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals. How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming

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38. Consider a CPU where all the instructions require 7 clock cycles to complete execution. There are 140 instructions in the instruction set. It is found that 125 control signals are needed to be generated by the control unit. While designing the horizontal micro-programmed control unit, single address field format is used for branch control logic. What is the minimum size of the control word and control address register?

  • Option : D
  • Explanation : As per question each instruction takes 7 cycles
    = 140 instructions will take = 140 * 7 cycles
    = 2m> = 980
    = m> = 10
    = 10 + 125 bits and 10 bits
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39. A CPU has only three instructions I1, I2 and I3, which use the following signals in time steps T1-T5.
I1 : T1 : Ain, Bout, Cin
T2 : PCout, Bin
T3 : Zout, Ain
T4: Pcin, BOut
T5 : End
I2 : T1 : Cin, Bout, Din
T2 : Aout, Ain
T3 : Zout, Ain
T4 : Bin, Cout
T5 : End
I3 : T1 : Din, Aout
T2 : Ain, Bout
T3 : Zout, Ain
T4 : Dout, Ain
T5 : End
Which of the following logic functions will generate the hardwired control for the signal Ain.

  • Option : A
  • Explanation : T1.I1 + T2.I3 + T4.I3 + T3
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40. A hardwired CPU uses 10 control signals S1 to S10 in various time steps T1 to T5 to implement 4 instructions I1 to I4 as shown below. Which of the following pairs of expressions represent the circuit for generating control signals S5 and S10 respectively [(IJ + Ik) Tn indicates that the control signals should be generated in time step Tn if the instruction being executed is IJ or lk]?

  • Option : D
  • Explanation : s5 = T1 + (I2 + I4).T3 and
    s10 = (I2 + I3).T2 + I4.T3 + (I1 + I3).T4 + (I2 + I4).T5
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