Computer System Architecture - Memory Hierarchy
- Option : A
- Explanation : Total address space = 32 bit
offset bit (B) = 5 bit
No. of bit to represent line no (L) = 9.
Tag bit + B + L = 32
= X + 5 + 9 = 32
= X = 18
- Option : B
- Explanation : Main Memory access time = 10–8 sec = (ta1)
Secondary Memo. access time = 10–3 sec = (ta2)
Access efficiency (n) = 80% = 0.8
Average Access time
tavg = n * ta1 = 0.8 × 10–3 sec
for Hit ratio H
tavg = H * ta1 + (1– H) * ta2
0.8 × 10–3 = H * 10–8 + (1 – H) * 10–3
0.8 = H × 10–5 + (1 – H)
H(1 – 10–5) = 0.2
H = 0.2/(1-10–5)
= 0.200002
= 20%
H = 20%
- Option : A
- Explanation : Each write request, the bus is occupied for 100 n.s
Storing of data requires 100 n.s.
In 100 n.s. – 1 store
100/106 n.s. = 1 store
1 m.s. = 106/100 stores =
10000 stores.
- Option : C
- Explanation : Given, total number of rows is 214 and time taken to perform one refresh operation is 50 nanoseconds.
So, total time taken to perform refresh operation
= 214 * 50 nanoseconds
= 819200 nanoseconds
= 0.819200 milliseconds.
But refresh period is 2 milliseconds.
So, time spent in refresh period in percentage
= (0.819200 milliseconds) / (2 milliseconds)
= 0.4096 = 40.96%
Hence, time spent in read/write operation
= 100% – 40.96% = 59.04% = 59
(in percentage and rounded to the closet integer).
