Computer System Architecture - Memory Hierarchy

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71. The cache hit ratio for this initialization loop is

Answer
Comment
Array

Option : C
Explanation : block size of cache = 16 bytes
element size = 8 bytes
During a memory access only the next element gets filled in the cache. i.e.; every alternative memory access is a cache miss giving a hit ratio of 50%.

A computer system has an L1 and L2 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively.

72. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?

Answer
Comment
Array

Option : D
Explanation : A block to access in L2 cache requires 20 nanoseconds, and 2 seconds to place in L1-cache. The block size in L1 cache is 4 words, and L2 block size is 16 words
So, total time = 4 * (time to access L2 + time to place in L1)<br / = 4 * (20 + 2) = 88 ns.

73. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?

Answer
Comment
Array

Option : D
Explanation : Since the block size of L2 cache is 16 words and the bandwidth of main memory * L2 cache is 4 words, it requires a transfer of 4 words 4 times and then a transfer of required 16 words from L2 cache to L1 cache.
So total time is 4 * (200 + 20) + 4 * (20 + 2)
= 968 nano seconds.

74. An 8KB direct-mapped write back cache is organized as multiple blocks, each of size 32 bytes. The processor generates 32 bit addresses. The cache controller maintains the tag information for each cache block comprising of the following.
1 Valid bit
1 Modified bit
As many bits as the minimum needed to identify the memory block mapped in the cache.
What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?

Answer
Comment
Array

Option : D
Explanation :

A computer has a 256 Kbytes, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.

75. The number of bits in the tag field of an address is

Answer
Comment
Array

Option : C
Explanation : Number of blocks = Cache-Size/Block-Size
= 256 KB/32 Bytes
= 2¹³
Number of Sets = 2¹³/4 = 2¹¹
Tag no. + Set no. + offset = 32
Tag + 11 + 5 = 32
Tag = 16 bit