Computer System Architecture - Memory Hierarchy

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A computer has a 256 Kbytes, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.

76. The size of the cache tag directory is

Answer
Comment
Array

Option : A
Explanation : Tag is 16 bit, 2 bit valid, 1 modified, 1 replace
Total bits for tag entry = 16 + 2 + 1 + 1 = 20
Size of tag array = 20 * no. of blocks
= 160 K bits.

77. An access sequence of cache block address of length N and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by k. What is the miss ratio if the access sequence is passed through a cache of associativity A * k exercising least-recently used replacement policy?

Answer
Comment
Array

Option : A
Explanation : Miss ratio = (Cache miss)/(No. of request)
= n/N

78. In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context ?

Answer
Comment
Array

Option : D
Explanation : When a cache block size is smaller, it could accommodate more number of blocks, it improves the hit ratio for cache, so the miss penalty for cache will be lowered.

79. In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 20% and the speed of a fixed point unit has been increased by 10%. What is the overall speedup achieved if the ratio of the number of floating point operations to the number of fixed point operations is 2 : 3 and the floating point operation used to take twice the time taken by the fixed point operation in the original design?

Answer
Comment
Array

Option : A
Explanation : Time taken by the original design
= (2n * 2t) + (3n * t)
= 7nt
Time taken by enhanced design
= (2n * 2t /1.2) + (3n * t/1.1)
= 6.06 nt
Speed up = 7 nt/6.06 nt
= 1.155

80. A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ............... bits.

Answer
Comment
Array

Option : A
Explanation : Type of mapping is direct map; for this direct map, 10 bits are required in its Tag. It is updated to 16 way set Associative map then new tag field size = 10 + log₂ 16 = 14 bits, because for k way set associative map design, log₂ k bits are additionally required to the number of bits in tag field for Direct map design.