Explanation : Here total 7 NAND gates are present and in half adder one AND and one EX-OR gate are required.
In turn one EX-OR gate can be built by 5 NAND
where as one AND gate can be built by 2 NAND gates
so this is diagram of half adder. So the answer is (D).
Explanation : Ans is A as input to 1st OR gate is A, and B' so output of 1st OR gate is (A+B') In the same way output for 2nd OR gate is (A'+B) So Final output will be (A+B')'. (A'+B)'