Computer Organization Architecture - I/O interface

1:   The 8085 microprocessor responds to the presence of an interrupt
A. As soon as the TRAP pin becomes 'LOW'
B. By checking the TRAP pin for 'high' status at the end of each instruction fetch
C. By checking the TRAP pin for 'high' status at the end of the execution of each instruction
D. By Checking the TRAP pin for 'high' status at regular intervals

Option: C

Explanation :


CPU has two modes privileged and non-privileged.In order to change the mode from privileged to non-privileged


A hardware interrupt is needed


A software interrupt is needed


Either (a) or (b)


A non-privileged instruction (which does not generate an interrupt) is needed


Option: B

Explanation :

A software interrupt is initiated by some program module which need  some CPU services, at that time the two modes can be interchanged. Hence (B) is correct option.

3:   The TRAP interrupt mechanism of the 8085 microposser executes
A. An RST by hardware
B. The instruction supplied by external device through the INTA signal
C. An instruction from memory location 20 H
D. None of these

Option: A

Explanation :

4:   Which of the following interrupts are unmaskable interrupts ?
A. RST 5.5
B. RST 7.5
D. Both (a) and (b)

Option: C

Explanation :

5:   The address range to which I/O chip will respond is
A. 0000 H to FFFF H
B. 0000 H to 5FFF H
C. 4000 H to 5FFFF H
D. None of these

Option: B

Explanation :

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Syllabus included in this section is-

  • Machine instructions and addressing modes
  • ALU and data-path
  • CPU control design
  • Memory interface
  • I/O interface (Interrupt and DMA mode)
  • Instruction pipelining
  • Cache and main memory
  • Secondary storage
  • Hardwired and Microprogrammed processor design
  • Instruction formats 
  • Addressing modes
  •  Memory types and organisation
  • Interfacing peripheral devices
  • Interrupts
  • Microprocessor architecture
  • Instruction set and Programming (8085, P-III/P-IV)
  • Microprocessor applications.

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