Computer System Architecture - Memory Hierarchy
- Option : B
- Explanation : RAM chip size = 1k * 8[1024 words of 8 bits each]
RAM to construct = 16k * 16
Number of chips required = (16k * 16)/(1k * 8)
= (16 * 2)
[16 chips vertically with each having 2 chips horizontally]
So to select one chip out of 16 vertical chips, we need 4 * 16 decoder.
Available decoder is 2 * 4 decoder
To be constructed is 4 * 16 decoder
Hence 4 + 1 = 5 decoders are required.
- Option : B
- Explanation : Input to ROM – 2 lines, 8 bit each.
Possible combinations in ROM – (2^8)*(2^8)
Size of truth table = (2^8)*(2^8)
= 2^16 = 64 KB
Maximum output size = 16 bit
68. The amount of ROM needed to implement at 4 bit multiplier is
- Option : D
- Explanation : For a 4 bit multiplier there are 24 * 24
= 28
= 256 combinations.
Output will contain 8 bits.
So the amount of ROM needed is 28 * 8bit s
= 2 Kbits.
Consider a machine a 2-way set associative data cache
of size 64 Kbytes and block size 16 bytes. The cache is
managed using 32 bit virtual addressed and the page
size is 4 Kybytes. A program to be run on this machine
begins as follows :
double APR {1024] [1024]
int i, j ;
/ * Initalize array APR to 0.0*/
for (i = 0; i < 1024; i ++)
for (j = 0; j < 1024; j++
APR [i] [j] = 0.0;
The size of double 8 bytes. Array APR is memory
starting at the beginning of virtual page 0 × FF000
and stored in row major order. The cache is initially
empty and no pre-fetching is done. The only data
memory references made by the program are those to
array APR.
69. The total size of the tags in the cache directory is
- Option : D
- Explanation : Virtual Address = 32 bits
Cache address is divided into TAG, SET, BLOCK
For BLOCK of 16 bytes, we need 4 bits.
Total number of sets(each set containing 2 Blocks)
= 64 KB/(2 * 16) B = 211
So, Number of SET bits = 11
Number of TAG bits = 32 – (11 + 4) = 17
So, cache address = 17 |11| 4 (TAG |SET| BLOCK)
Tag memory size
= Number of tag bits * Total number of blocks
= 17 * 2 * 211 (Total Number of blocks
= 2 * Total number of sets)
= 68 KB
Consider a machine a 2-way set associative data cache
of size 64 Kbytes and block size 16 bytes. The cache is
managed using 32 bit virtual addressed and the page
size is 4 Kybytes. A program to be run on this machine
begins as follows :
double APR {1024] [1024]
int i, j ;
/ * Initalize array APR to 0.0*/
for (i = 0; i < 1024; i ++)
for (j = 0; j < 1024; j++
APR [i] [j] = 0.0;
The size of double 8 bytes. Array APR is memory
starting at the beginning of virtual page 0 × FF000
and stored in row major order. The cache is initially
empty and no pre-fetching is done. The only data
memory references made by the program are those to
array APR.
70. Which of the following array elements has the same cache index as APR [0] [0] ?
- Option : B
- Explanation : ARR[0][0] i s located at virtual address 0xFF000000. Here FF000 is page address and 000 is page offset. So, index bits are 00000000000 Address of ARR[4][0] = 0xFF000 + 4 * 1024* size of (double) [since we use row major storage] = 0xFF000000 + 4096 * 8 = 0xFF000000 + 0x8000 = 0xFF008000 ( index bits matches that of ARR[0][0] as both read 00000000000)
