Computer System Architecture - Memory Hierarchy

51. The principle of locality justifies the use of

  • Option : D
  • Explanation : Cache memory is placed between main memory and CPU.
Cancel reply

Your email address will not be published. Required fields are marked *


Cancel reply

Your email address will not be published. Required fields are marked *


52. A graphics card has on board memory of 1 MB. Which of the following modes can be card not support?

  • Option : B
  • Explanation : A disk driver is software which enables communication between internal hard disk (or drive) and computer.
    It allows a specific disk drive to interact with the remainder of the computer.
Cancel reply

Your email address will not be published. Required fields are marked *


Cancel reply

Your email address will not be published. Required fields are marked *


53. Which of the following requires a device driver?

  • Option : D
  • Explanation : Exploit the spatial locality of reference in a program as, if the next locality is addressed immediately, it will already be in the cache.
Cancel reply

Your email address will not be published. Required fields are marked *


Cancel reply

Your email address will not be published. Required fields are marked *


54. More than one word are put in one cache block to

  • Option : B
  • Explanation : Statement I is not necessary because at the same point of time, data need not to be exactly same. Therefore, write back policy can also be used.
    Statement I I i s not necessary when when discussing only about L1 and L2.
    Statement I I I i s not necessary because associativity can be equal.
    Statement IV is necessary, The L2 cache must be at least as large as the L1 cache.
Cancel reply

Your email address will not be published. Required fields are marked *


Cancel reply

Your email address will not be published. Required fields are marked *


55. For inclusion to hold between two cache level L1 and L2 in a multilevel cache hierarchy, which of the following are necessary?
1. L1 must be a write-through cache
2. 2 must be a write-through cache
3. The associativity of L2 must be greater that of L1
4. The L2 cahce must be at least as large as the L1 cache

  • Option : A
  • Explanation : Number of sets in cache = v. So, main memory block j will be mapped to set (j mod v), which will be any one of the cache lines from (j mod v) * k to (j mod v) * k + (k – 1).
Cancel reply

Your email address will not be published. Required fields are marked *


Cancel reply

Your email address will not be published. Required fields are marked *


Related Quiz.
Memory Hierarchy