Gate2020 cs Q51

51Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipeline processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instruction. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipeline processor (round off to 2 decimal places) is ______.

Note – Numerical Type question

Option : B
Explanation :
Non-pipeline
Clock frequency = 2.5 GHz.
Cycle time = 1/2.5 GHz = 0.4ns
Given, CPI = 5
So, ET_non-pipe = CPI × Cycle time
= 5 × 0.4 ns = 2 ns
Pipeline:
Clock frequency = 24 GHz
Cycle time = 1/2 GHz = 0.5ns

∴ Number of stalls/instruction = 0.3 × 0.05 × 50 + 0.1 * 0.5 × 2
= 0.85
Avg. instruction ETpipe = (1 + No. of stall instruction) * cycle time
= (1 + 0.85) × 0.5 ns = 0.925 ns

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