Gate2019 cs Q55

55A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is __________× 10⁶ bytes/sec.

Note – Numerical Type question

Option : A
Explanation :
Total time to transfer a cache block = 1 + 3 + 8 = 12 cycles
8 W _____________ 12 cycles
8 × 4 bytes ________________ 12 cycles
? B _____________ 1 sec

= 160 x 10⁶

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