Gate2017 cs Q44

0. Instructions execution in a processor is divided into 5 stages. Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2ns. Two pipelined implementations of the processor are contemplated.
(i) a naïve pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage id divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimals places) achieved by EP over NP in executing 20 independent instructions with no hazards is _____.

Note – Numerical Type question

Answer
Comment
Array

Option : A
Explanation :
Given,
For Navie pipeline (NP)
Number of stages (k) = 5
T_p = max (stage delay + buffer delay)
T_p = max 7, 6, 22, 12, 5 = 22 n sec.
Number of instructions (n) = 20
So, erection time for navie pipeline
ET_NP = k + (n −1) × T_p = 5 + 20 −1 × 22 = 528n sec
Now, for efficient pipeline
k = 6, n = 20, T_p = 14nsec.
E_EP = k + (n −1) ×T_p = 6 + 20 −1 ×14 = 350n sec.
Therefore, Speedup = 528/350= 1.508

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