Gate2017 cs Q18

18Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is _____.

Note – Numerical Type question

Option : A
Explanation :
Number of memory access in 1000 instructions = 1.4 x 1000
= 1,400
∴ Miss rate = 7/(1400 x 0.1) = 0.05

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