info@avatto.com
+91-9920808017
Delayed branching can help in the handling of control hazardous
0. The following code is to run on a pipelines processor with one branch delay slot I1 : ADDR2 ⇽ R7 + R8 I2 : SIN R4 ⇽ R5 – R6x I3 : ADD R1 ⇽ R2 + R3 I4 : STORE Memory [R4] ⇽ R1 BRANCH to Label if R1 == 0 Which of the instruction 11, 12, 13 or 14 can legitimately occupy the delay slot without any other program modification?
11
12
13
14
You must be logged in to post a comment.
Login with Facebook
Login with Google
Forgot your password?
Lost your password? Please enter your email address. You will receive mail with link to set new password.
Back to login
You must be logged in to post a comment.